'Moore's Law is running out of gas'

IBM Corp. Fellow Carl Anderson, who oversees physical design and tools in its server division, predicted during a recent conference the end of continued exponential scaling down of the size and cost of semiconductors. The end of the era of Moore's Law, Anderson declared, is at hand.
Anderson was one of 65 semiconductor gurus speaking at the International Symposium on Physical Design 2009, which also unveiled a new method for synthesising critical paths, a host of analogue design innovations and a new twist on the annual physical design contest.

The IBM Fellow observed that like the railroad, automotive and aviation industries before it, the semiconductor industry has matured to the point that the pace of continued innovation is slowing.

"There was exponential growth in the railroad industry in the 1800s; there was exponential growth in the automobile industry in the 1930s and 1940s; and there was exponential growth in the performance of aircraft until [test pilots reached] the speed of sound. But eventually exponential growth always comes to an end," said Anderson.

A generation or two of continued exponential growth will likely continue only for leading-edge chips such as multi-core microprocessors, but more designers are finding that everyday applications do not require the latest physical designs, Anderson said.

Consequently, Moore's Law—halving of the dimensions and doubling of speed of chips every 18 months—will run out of steam very soon. Only a few high-end chipmakers today can even afford the exorbitant cost of next-generation research and design, much less the fabs to build them.

Anderson cited three next-generation technologies that were still on the fast track for exponential growth: optical interconnects, 3D chips and accelerator-based processing. He predicted that rack-to-rack optical interconnects will become commonplace, with chip-to-chip optical connections on the same board coming soon. But Anderson said on-chip optical signalling remains years away.

He also predicted that stacked DRAM dies would be the first to go 3D.

Synthesising a critical path
The conference's best paper award went to researcher Qunzeng Liu and Professor Sachin Sapatnekar of the University of Minnesota, The paper described their method of synthesising a critical path during design process that could then serve as a representative for post-silicon delay prediction. The representative critical path could serve as a "canary in a coal mine" for tuning post-silicon yield enhancement, they said. "With the increasing variability concerns and performance deviation due to the variability in advanced technologies," said Gi-Joon Nam, the conference general chair, "post-silicon analysis and optimisation is attracting attention to actually measuring variability in order to improve the performance of silicon."

Nam added that the research "can be extremely useful, particularly in high-end technology nodes with significant variations."

Simulations predict less than 3 per cent prediction errors when synthesising a representative critical path (RCP). Sapatnekar's group plans to test their techniques on silicon chips to confirm the effectiveness of RCPs.

Analogue design innovation
Experts from Magma Design Automation, Taiwan Semiconductor Manufacturing Co. and Bosch predicted that the rapid pace of analogue design innovation would continue. Magma's Anirudth Devgan described a method for abstracting analogue block designs with parameterised, model-based analogue design acceleration. Devgan said automatic place-and-route tools were best used only at the top level of analogue and mixed-signal blocks, rather than at the individual block level.

Eric Soenen, director of TSMC's Austin Design Center, said the most critical aspect of analogue design was good layout techniques, especially those using smart matching, shielding and spacing techniques.

Bosch's Goeran Jerke described a formal framework for increasing the efficiency and degree of automation for analogue design tools by representing abstract constraints and automatically transforming them to lower-level design constraints.

A new twist on the annual design contest this year was a clock network synthesis task. Twenty-seven teams (16 from the United States) entered, but only nine survived.

"Research in EDA tools for clock synthesis is not as popular as other areas such as placement or routing," said Phillip Restle, a research staff member at IBM's Watson Research Center. "However, clock design automation is actually much more difficult."

The task involved distributing a 2GHz clock across a chip with picosecond precision. IBM evaluated the submissions using seven benchmarks derived from its most recent 45nm designs. It verified results with electrical circuit simulations using open-source tools and the Predictive Technology Model created at Arizona State University.

Of the three winning entries, one came from the United States: "Contango", written by Dongjin Lee, a graduate student working in the lab of Professor Igor Markov at the University of Michigan.

"The contest was based on Spice simulation, and we found that even the state-of-the-art analytical models were not accurate enough," said Markov. "We had to put Spice inside our optimisation flow."

The two other winning teams were National Taiwan University and National Chiao-Tung University.

"This contest is a first step towards capturing concerns of industrial clock synthesis, targeting rough estimates for real clock skew using Spice simulations subject to power and slew constraints," said Rupesh Shelar, a senior component design engineer at Intel Corp.

Prashant Saxena, the conference programme chair and principal engineer at Synopsys, said the new clock synthesis contest should spur new research into areas neglected using more conservative clocking methodologies. The result, Saxena said, will be better algorithms and more highly automated clocking flows.

BY R. Colin Johnson
Source:EE Times

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