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22nm-generation transistors based on existing volume-production technology also appeared. While there are some remaining problems to be resolved with photolith technology and other details, it is clear that Moore's Law - once feared to have been headed for extinction - is picking up speed again, and is back on track for the time being. About 700 people crowded Session 27, on next-gen CMOS technology, and there was an active exchange of information and opinions.
Issues: 22nm-Gen SRAM
The first presentation in Session 27 was on 22nm-generation static random-access memory (SRAM) (Paper 27.1; Fig 1), by a group of three firms: IBM Corp of the US, Advanced Micro Devices Inc (AMD) of the US, and Freescale Semiconductor Inc of the US. The transistor architecture was not anything special like FinFET or tri-gate, but used almost entirely existing technology with the exception of HKMG. Even better, it was developed using 300mm wafer volume production equipment.
The SRAM has six transistors, with a minimum gate length of 22nm, and a gate pitch of 90nm, which IBM described as "dramatically reduced." As a result, again according to IBM, the SRAM's area is "the world's smallest" at only 0.09um2. Static noise margin (SNM), an index of SRAM performance, measured for a chip with a 0.1um2 area, was 220mV at 1V supply, and 160mV at 1V supply for a chip with a 0.09um2 area: both pretty good numbers.
Drive current, which determined SRAM operating speed, however, is admittedly (again, according to IBM) very low - only just under 0.3mA/um at 1.0V supply for NMOS, making immediate commercial application impossible (Table 1). One semiconductor researcher from Japan commented, "The key priority was to get a 22nm-generation technology.
Performance comes later." IBM explained, "This SRAM is only the first prototype of 22nm-generation technology. It doesn't use strained Si technology, and the device hasn't been optimized at all. We'll improve the drive current."
HKMG: Industry Standard
The 32nm-generation CMOS technologies presented during Session 27 are all close to the volume-production level, and much closer to commercial roll-out than 22nm. All of the presentations used HKMG. Prof Shinichi Takagi of University of Tokyo, Japan, explained that HKMG alleviates the problem with manufacturing process technology that dielectric films cannot be made sufficiently thin, at least for now. In fact, all of the firms use dielectric films significantly thinner than those of the prior generation, in SiO2 (equivalent oxide thickness) terms, providing a major increase in On current (Note 1).
Intel Maintains 32nm Lead
Intel Corp of the US was the first firm to adopt HKMG, in a 45nm-generation microprocessor, and is still in the lead when it comes to 32nm. The SRAM presented by the firm has an On current of 1.55mA/um at 1V supply for NMOS, or 1.21mA/um for PMOS (Paper 27.9), described by one engineer in the field as "...astonishingly high." Yield, according to a source at Intel, "...is improving right on schedule, two years behind the prior generation, as always." The company plans to begin volume production of microprocessors using 32nm technology in the second half of 2009.
Intel's technology is very interesting for more than just performance, because it offers a path to 22nm-generation manufacturing. Intel is the only major semiconductor manufacturer to use the "last gate" technique. The poly-Si gate electrode is formed first, then the source and drain electrodes, and then finally the gate electrode is replaced with a metal gate electrode. Most other firms use the "first gate" technique, directly forming the metal gate before the source or drain.
The first gate method is very compatible with existing manufacturing technology, and is generally expected to facilitate the transition to smaller geometries because of the simplicity of the processing.
Intel has said that it uses the last gate approach because it can deliver the maximum effectiveness for strained Si technology. The company has previously, however, admitted that the technique poses problems in fabrication ease, ease of transition to 22nm and other points. This time, though, Intel claimed that it has "...overcome the problems of the last gate technique."
TSMC as the Third Pole
A third party is trying to force its way into the competition between the IBM group and Intel: Taiwan Semiconductor Manufacturing Co Ltd (TSMC) of Taiwan. At IEDM 2007 the company announced a 32nm-generation technology that did not use HKMG, but this time it adopted the technology to skip 32nm entirely and prototype a 28nm-generation SRAM (Paper 27.2).
Minimum gate length is only 24nm, shorter than that of IBM's 22nm-generation design, but even so the On current is almost as great as that of the 32nm-generation chip from Intel. In October 2008 TSMC announced that it would begin volume production using 28nm-generation technology in the third quarter of 2010. The speaker commented, "Development is proceeding on schedule toward volume production." Until now the firm has been in the news for its low cost, but it has emerged as a company to watch for cutting-edge technology in microfabrication, too.
Note 1: For example, Intel has used HKMG in a 45nm SoC as well as in the 32nm logic IC. Concerning the SoC implementation, Intel commented, "The reduced leakage current made it possible to achieve an On current 57% higher than the 65nm implementation."
* High-k/metal gate (HKMG) technology: this technology utilizes hafnium (Hf) or other material with high permittivity as the dielectric film, replacing conventional SiO2 or SiON, and switches from poly-Si to metal for the gate electrode. The higher gate electric permittivity allows a physically thicker structure, which reduces leakage current.
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BY Nikkei Electronics Asia
Source：nikkeibp.co.jp
Copyright © 1995-2009 Nikkei Business Publications, Inc. All rights reserved.
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