Chip features shrink to 32 nanometres

Industry giant Intel Corporation says it has completed the development phase of its next-generation manufacturing process that further shrinks chip circuit features to 32 nanometres. The company is on track for production readiness of this future generation using more energy-efficient, denser and higher performing transistors in the fourth quarter of 2009.
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The company provided technical details of 32 nm process technology at the International Electron Devices Meeting (IEDM) held recently in San Francisco, CA, USA. The 32 nm development is part of a plan by Intel to introduce an entirely new processor microarchitecture alternating with a cutting edge manufacturing process about every 12 months. Producing 32nm chips next year would mark the fourth consecutive year the company has met its goal.

The 32 nm paper and presentation describe a logic technology that incorporates second-generation high-k + metal gate technology, 193 nm immersion lithography for critical patterning layers and enhanced transistor strain techniques. These features enhance the performance and energy efficiency of Intel processors. The company claims its manufacturing process has the highest transistor performance and the highest transistor density of any reported 32 nm technology in the industry.

“Our manufacturing prowess and resulting products have helped us widen our lead in computing performance and battery life for Intel-based laptops, servers and desktops,” says Mark Bohr, Intel Senior Fellow and director of process architecture and integration. “As we’ve shown this year, the manufacturing strategy and execution have also given us the ability to create entirely new product lines for MIDs, CE equipment, embedded computers and netbooks.”

Other Intel IEDM papers presented at the meeting described a low power system on chip version of the company’s 45 nm process, transistors based on compound semiconductors, substrate engineering to improve performance of 45 nm transistors, integrating chemical mechanical polish for the 45 nm node and beyond; and, integrating an array of silicon photonics modulators.

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Source：Electronics NEWS

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